The present invention is generally directed to voltage protection devices and, more specifically, to the use of test multiplexers having over voltage protection and methods of operating the same in an integrated circuit.
In microelectronic circuit design there is an increasing demand for low-power, low-voltage circuits. Complementary metal-oxide semiconductor (CMOS) devices operate at high switching speeds and with high packing densities, even with a comparatively low voltage power supply. However, device dimensions in integrated circuits are now becoming so small that their isolation barriers may break down at just a few volts.
CMOS integrated circuits use n-type and p-type metal oxide field effect transistors (MOSFET) that may have a gate, a drain, or a source terminal connected to a signal line driven by another circuit. A longstanding problem is that electrostatic discharges (or similar externally generated voltage transients) may break down the thin gate oxide of the CMOS transistor. Once the gate oxide has been damaged, the transistor may be useless. A similar problem may arise in systems using multiple voltage levels. In this case, not only is there a risk of electrostatic discharge but an over-voltage may occur in a low voltage circuit. An external signal line of the regulated lower voltage system may be coupled to a higher voltage pin. Under some operating conditions, xe2x80x9clatch upxe2x80x9d may occur. Consequently, there is a significant risk of damage to the low-voltage components in an integrated circuit due to an over-voltage condition.
A typical CMOS integrated circuit includes a test multiplexer (MUX) that may be engaged by program logic to test the operation of individual circuits within the CMOS integrated circuit. A typical CMOS integrated circuit may be set at Vcc/2(1.5 V) where Vcc is the supply voltage (typically 3 volts). Normally, a regular CMOS test MUX would serve the purpose of over-voltage protection because at no time would the signal at the source or drain of a p-type or n-type device in the test mux exceed the gate voltage by more than the breakdown threshold voltage. However, in certain types of CMOS circuits, peak voltage may be as high as five volts. At five volts, a p-type or n-type device on a CMOS test mux may easily latch up since the voltage difference between the gate and source, the gate and drain, or the gate and bulk would be five volts, which is greater than the breakdown voltage.
There is therefore a need in the art for an over-voltage protection circuit that does not latch up in response to input over-voltages.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a test multiplexer having (i) a plurality of MOSFET devices that cooperate to pass an input signal to an output signal line when the test multiplexer is enabled, and (ii) over voltage protection circuitry that is biased so that a difference between the input signal voltage and a bias voltage does not exceed breakdown when the test multiplexer is disabled.
According to one advantageous embodiment, the plurality of MOSFET devices comprises at least one p-type MOSFET device and at least one n-type MOSFET device, and the over voltage protection circuitry comprises a bias circuit. When the test multiplexer is enabled (i.e., during xe2x80x9ctest modexe2x80x9d), the p-type and n-type MOSFET devices cooperate to pass a first input signal to an output signal line of the test multiplexer.
In contrast, when the test multiplexer is disabled (i.e., xe2x80x9coff modexe2x80x9d), the bias circuit of the over voltage protection circuitry operates to generate a reference voltage that is not more than a breakdown threshold voltage, Vt, below a maximum signal level on the first signal line. This reference voltage is applied to at least one of a gate, a drain, a source and a bulk connection of the at least one p-type MOSFET device such that none of a first voltage difference between the gate and the drain, a second voltage difference between the gate and the source, and a third voltage difference between the gate and the bulk connection is greater than the breakdown threshold voltage, Vt.
According to a related embodiment, the reference voltage is further applied to at least one of another gate, another drain, another source and another bulk connection of the at least one n-type MOSFET device such that none of a first voltage difference between the another gate and the another drain, a second voltage difference between the another gate and the another source, and a third voltage difference between the another gate and the another bulk connection is greater than the breakdown threshold voltage, Vt.
An important aspect hereof is that the test multiplexer is operable to provide over-voltage protection that is compliant to input voltages that exceed the positive supply rail. In an exemplary embodiment discussed hereafter, the test multiplexer is composed of p-type and n-type MOSFET devices, wherein most of the p-type MOSFET devices are tied to source, and at least two n-type MOSFET devices are connected in series and biased so that terminal voltages do not exceed breakdown. This exemplary test multiplexer is capable of sustaining single ended voltages as high as five volts at an input signal line without latching up.
In another related embodiment, the over voltage protection circuitry of the test multiplexer is capable of sampling another input signal on an input signal line that one of enables and disables said test multiplexer. The bias circuit thereof is operable to generate a reference voltage that is not more than a breakdown threshold voltage, Vt, below a maximum signal level on the input signal line, the over voltage protection circuitry is further operable to disable the bias circuit in response to the sampled another input signal enabling the test multiplexer.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor, xe2x80x9d is inclusive, meaning and/or; and the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Further definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.